The present invention relates generally to the field of microelectronics, and more specifically to housing of microelectronic devices in a package having an integral window.
Many different types of microelectronic devices require a transparent window to provide optical, UV, and IR access; as well as protection from the environment. Examples of light-sensitive semiconductor devices include charge-coupled devices (CCD), photosensitive cells (photocells), solid-state imaging devices, and UV-light sensitive Erasable Programmable Read-Only Memory (EPROM) chips. All of these devices use microelectronic devices that are sensitive to light over a range of wavelengths, including ultraviolet, infrared, and visible light. Other types of semiconductor photonic devices emit photons, such as laser diodes, light emitting diodes (LED""s), and Vertical Cavity Surface-Emitting Laser (VCSELS), which also need to pass light through a protective window.
Microelectromechanical systems (MEMS) and Integrated MEMS (IMEMS) devices (e.g. MEMS devices combined with Integrated Circuit (IC) devices) can also require a window for optical access. Examples of MEMS devices include airbag accelerometers, microengines, microlocks, optical switches, tiltable mirrors, adaptive mirror membranes, micro reflectors (retro-reflectors), micro reflectors with micro-shutters, miniature gyroscopes, sensors, and actuators. All of these MEMS devices use active mechanical and/or optical elements. Some examples of active MEMS structures include gears, hinges, levers, slides, tilting mirrors, optical sensors. These active structures must be free to move, rotate, or interact with light or other photonic radiation. Optical access through a window is required for MEMS devices that have mirrors and optical elements. Optical access to non-optically active MEMS devices can also be required for permitting visual inspection, observation, and/or performance characterization of the moving elements.
Additionally, radiation detectors that detect alpha, beta, and gamma radiation, use opaque xe2x80x9cwindowsxe2x80x9d of varying thickness and materials that transmit, block, or filter these energetic particles. These devices also have a need for windows that transmit or filter radiation to and from the active device, while at the same time providing physical.
There is a continuing need in the semiconductor fabrication industry to reduce costs and improve reliability by reducing the number of fabrication steps, while increasing the density of components. One approach is to shrink the size of packaging. Another is to combine as many steps into one by integrating operations. A good example is the use of cofired multilayer ceramic packages. Unfortunately, adding windows to these packages typically increases the complexity and costs.
Hermetically sealed packages are used to satisfy more demanding environmental requirements, such as for military and space applications. The schematic shown in FIG. 1 illustrates a conventional ceramic package for a MEMS device, a CCD chip, or other optically active microelectronic device. The device or chip is die-attached face-up to a ceramic package and then wirebonded to interconnect inside of the package. Metallized circuit traces carry the electrical signal through the ceramic package to electrical leads mounted outside. A glass window is attached as the last step with a frit glass or solder seal. Examples of conventional ceramic packages include Ceramic Dual In-Line Package (CERDIP), EPROM and Ceramic Flatpack designs.
Although stronger, ceramic packages are typically heavier, bulkier, and more expensive to fabricate than plastic molded packages. Problems with using wirebonding include the fragility of very thin wires; wire sweep detachment and breakage during transfer molding; additional space required to accommodate the arched wire shape and toolpath motion of the wirebond toolhead; and the constraint that the window (or cover lid) be attached after the wirebonding step. Also, attachment of the window as the last step can limit the temperature of bonding the window to the package. Finally, vapors emitted by polymer-based adhesives used to fasten the window can be deposited on released MEMS structures, causing problems with stiction.
FIG. 2 illustrates schematically a conventional molded plastic (e.g. encapsulated) microelectronic package. The chip is attached to a lead frame, and a polymer dam (e.g., epoxy) prevents the plastic encapsulant from flowing onto the light-sensitive active area of the chip during transfer molding. The window is attached with a polymer-based adhesive (e.g., an epoxy-based adhesive, a polyimide-based adhesive, a silicone-based adhesive, an acrylic-based adhesive, or a urethane-based adhesive). This type of package is not hermetic against moisture intrusion, cannot be used for high temperature operation, and the use of plastics and adhesives can interfere with the operation of MEMS structures.
Flip-chip mounting (i.e., interconnecting) of semiconductor chips is an attractive alternative to wirebonding. In flip-chip mounting,.the chip (i.e., device) is mounted facedown and then electrically interconnected to circuit traces on the substrate via xe2x80x9cbumpsxe2x80x9d (e.g., balls, bumps, pads). The bumps can be made of gold, aluminum, copper, or solder, and can be joined using reflow soldering, plasma-assisted dry soldering, thermocompression bonding, ultrasonic bonding, or thermosonic bonding. All of the flip-chip interconnections are made simultaneously. Excess spreading of a molten solder ball/bump is prevented by the use of specially designed bonding pads. Flip-chip mounting has been successfully used in fabricating Multi-Chip Modules (MCM""s), Chip-on-Board, Silicon-on-Silicon, and Ball Grid Array packaging designs.
Flip-chip mounting has many benefits over traditional wirebonding, including increased packaging density, lower lead inductance, shorter circuit traces, thinner package height, no thin wires to break, and simultaneous mechanical die-attach and electrical circuit interconnection. Another advantage is that the chips are naturally self-aligning due to favorable surface tension when using molten solder balls/bumps. It is also possible to replace the metallic solder bumps with bumps, or dollops, of an electrically-conductive polymer or epoxy (e.g. silver-filled epoxy). Flip-chip mounting avoids potential problems associated with ultrasonic bonding techniques that can impart stressful vibrations to a fragile (e.g. released) MEMS structure. A polymer underfll can be optionally applied to the rows of interconnected bumps to provide additional mechanical strength, and to improve reliability.
Despite the well-known advantages of flip-chip mounting, this technique has not been widely practiced for packaging of MEMS devices, Integrated MEMS (IMEMS), or CCD chips because attaching the chip facedown to a solid, opaque substrate prevents optical access to the optically active or photonically interactive surface.
The use of multilayered materials in electronic device packaging has a number of advantages. Each individual layer (i.e., ply or sheet) of dielectric material can be printed with electrically conducting metallic traces, and the traces on different levels can be interconnected by conductive paths (i.e., vias) that cut across the laminated layers. Each layer can be individually xe2x80x9cpersonalizedxe2x80x9d by cutting unique patterns of cutouts in the layer, that, when stacked with other xe2x80x9cpersonalizedxe2x80x9d layer, can create a complex internal three-dimensional structure of cavities, recesses, etc. Multilayered materials include laminated polymer-based printed circuit board, materials, and laminated ceramic-glass composite materials.
The cost of fabricating ceramic packages can be reduced by using cofired ceramic multilayered packages. Multilayered packages are presently used in many product categories, including leadless chip carriers, pin-grid arrays (PGA""s), side-brazed dual-in-line packages (DIP""s), flatpacks, and leaded chip carriers. Depending on the application, 5-40 layers of dielectric layers can be used, each having printed signal traces, ground planes, and power planes. Each signal layer can be connected to adjacent layers above and below by conductive vias passing through the dielectric layers at right angles to the plane of the layers.
Electrically conducting metallized traces, thick-film resistors, and conductive vias or Z-interconnects are conventionally made by thin-film or thick-film metallization techniques, including screen-printing, microjet printing, or etched foil methods. The multiple layers are printed, vias-created and filled, layers collated and registered. The layers are then joined together and permanently bonded at elevated temperature and pressure to form a rigid assembly.
For co-fired ceramic-based substrates, the process comprises lamination at a low temperature and high pressure; then burnout at an intermediate temperature, followed by firing at a high temperature. Burnout at 350-600 C. removes the organic binders and plasticizers from the substrate layers and conductor/resistor pastes. After burnout, these parts are fired at much higher temperatures, which sinters and devitrifies the glass-ceramic composite to form a dense, flawless, and rigid insulating structure. During firing, glass-forming constituents in the layers can flow and fill-in voids, corners, and join together adjacent or mating surfaces that are wetted by the molten glass-forming constituents.
Two different cofired ceramic systems are conventionally used, depending on the choice of materials: high-temperature cofired ceramic (HTCC), and low-temperature cofired ceramic (LTCC). HTCC systems typically use alumina substrates; are printed with molybdenum-manganese or tungsten conducting traces; and are fired at high temperatures, from 1300 C. to 1800 C. LTCC systems use a wide variety of glass-ceramic substrates; are printed with Au, Ag, or Cu metallizations; and are fired at lower temperatures, from 600 C. to 1300 C. After firing, the semiconductor die is attached to the fired HTCC (or LTCC) body; followed by wirebonding. Finally, the package is lidded and sealed by attaching a metallic, ceramic, or glass cover lid with a braze, a frit glass, or a solder seal, depending on the hierarchy of thermal processing and on performance specifications.
Use of cofired multilayer ceramic structures for semiconductor packages advantageously permits a wide choice of geometrical designs, cutout shapes, recessed cavities, and processing conditions, as compared to previous use of bulk ceramic pieces (which typically had to be cut and ground from solid blocks or bars, a tedious and expensive task). Ceramic packages with high-temperature seals are generally stronger and have improved hermeticity compared to plastic encapsulated packages. It is well known to those skilled in the art that damaging moisture can penetrate polymer-based seals and adhesive joints over time. Also, metallized conductive traces are more durable than freestanding wirebond segments, especially when the traces are embedded and protected within a layer of insulating material (e.g., in LTCC/HTCC packages).
The order in which the window is attached during the fabrication sequence is important. Conventional methods attach the window (or cover lid containing a window) to the package with an polymer-based adhesive after completing the steps of die attachment and wirebonding of the chip or MEMS device to the package. However, the fragile released MEMS structures are exposed to particulate contamination, mechanical stress, and electrical (static) damage during die attachment and wirebonding.
What is needed is a packaging process that minimizes the number of times that a MEMS device is handled and exposed to temperature cycles and different environments, which can possibly lead to contamination of the device. It is highly desirable, therefore, that as many of the package fabrication steps as possible are performed before mounting and releasing the MEMS device. What is needed, then, is a packaging process that attaches the window to the package before mounting the device to the package. It is also desired that the window be attached to the package body at a high temperature to provide a strong, hermetic bond between the window and the body, and to survive subsequent elevated temperature operations (e.g. lid sealing, soldering, etc.) in the hierarchy of temperature processing steps during fabrication. What also is needed is a method where the MEMS structures on the device face away from the cover lid, so that contamination is reduced when the cover lid is attached as the last step.
Electrical interconnections from the chip to the package are needed that are stronger and less fragile than conventional wirebonds. What also is needed is a package having a high degree of strength and hermeticity.
In some applications, it is also desired to stack back-to-back multiple chips, possibly of different types (e.g. CMOS, MEMS, etc.) inside of a single package containing one or more windows. This increases the packing density, which is highly desirable to reduce costs and size.
The present invention relates to a bi-level, monolithic multilayered package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).